Bypassing Scheme for Inclusive Last Level Caches

The design of an effective last level cache(LLC) continues to be an important issue in processor‘s performance. Recent works on high performance caches have shown that cache bypassing is an effective technique to enhance the performance of last level caches. However, commonly used inclusive cache hierarchy cannot benefit from this technique because bypassing inherently breaks the inclusion property. This paper presents a solution to enabling cache bypassing for inclusive caches. It introduces a bypass buffer to an LLC. Bypassed cache lines skip the LLC while their entries are allocated into the bypass buffer. And it is a simple, low-hardware overhead, yet effective, cache bypassing scheme that dynamically chooses which blocks to insert into the LLC and which blocks to bypass it based on past access/bypass patterns on a miss. Our proposed scheme is evaluated using a detailed simulation environment where its effectiveness, performance-improvement capabilities, and robustness are demonstrated. We present experimental results showing IPC(Instruction Per Cycle) comparison of the proposed scheme and OBM(Optimal Bypass Monitor) against LRU for SPEC CPU2006 benchmarks. The result show that the proposed scheme and OBM can improve IPC by an average of 18% and 14%, respectively. And the proposed scheme reduces the miss rate by 16% compared to LRU. C 2016 KKITS All rights reserved K E Y W O R D S : LLC(last-level cache), Cache bypassing, Inclusive caches, Exclusive caches, Bypass buffers A R T I C L E I N F O : Received 23 March 2016, Revised 11 April 2016, Accepted 11 April 2016. Corresponding author is with the Department of Computer Science, University of Suwon, 17 Wauangil Bongdam-Eup Hwaseong-Si, Gyeonggi-Do, 18323, KOREA. E-mail address: [email protected] Journal of Knowledge Information Technology and Systems(JKITS), Vol. 10, No. 2, pp. xx~xx, April 2016